Innovation Watch - Latest UM Patents (2026-07-27)
A millimeter wave phase-locked loop
一種毫米波鎖相環
Publication No.:
CN122457044A
Publication Date:
2026-07-27
Applicant(s):
澳門大學; University of Macau
Inventor(s):
李浩然；殷俊；麥沛然；馬許願; Li Haoran; Yin Jun; Mai Peiran; Rui Paulo da Silva Martins
Technology Field(s):
基本通訊流程、測量; Basic communication processes, Measurement
The present invention discloses a millimeter-wave phase-locked loop, comprising: a feedback-loop phase-locked loop formed by a subsampling phase detector, a voltage-controlled oscillator, a proportional-path unit, a voltage comparator, and an integrating-path unit; a digital logic circuit configured to generate a gain control signal, a first control word, a second control word, and a selection signal according to a frequency control word and a phase-error signal; a digital-to-time converter configured to generate a delay signal according to a reference signal, the gain control signal, and the first control word; an auxiliary digital-to-time converter configured to compensate for a duty-cycle error according to the delay signal and the second control word and to generate a digital output signal; and a clock-generation circuit configured to generate a plurality of sampling clock signals according to the digital output signal. The subsampling phase detector performs rising-edge sampling and falling-edge sampling on an output signal of the voltage-controlled oscillator according to the plurality of sampling clock signals and the selection signal. Embodiments of the present invention achieve extremely low jitter and low in-band fractional spurs while occupying a very small area, and may be widely applied in the field of electronic circuit technology.
Publication No.:
CN122457044A
Publication Date:
2026-07-27
Applicant(s):
澳門大學; University of Macau
Inventor(s):
李浩然；殷俊；麥沛然；馬許願; Li Haoran; Yin Jun; Mai Peiran; Rui Paulo da Silva Martins
Technology Field(s):
基本通訊流程、測量; Basic communication processes, Measurement
The present invention discloses a millimeter-wave phase-locked loop, comprising: a feedback-loop phase-locked loop formed by a subsampling phase detector, a voltage-controlled oscillator, a proportional-path unit, a voltage comparator, and an integrating-path unit; a digital logic circuit configured to generate a gain control signal, a first control word, a second control word, and a selection signal according to a frequency control word and a phase-error signal; a digital-to-time converter configured to generate a delay signal according to a reference signal, the gain control signal, and the first control word; an auxiliary digital-to-time converter configured to compensate for a duty-cycle error according to the delay signal and the second control word and to generate a digital output signal; and a clock-generation circuit configured to generate a plurality of sampling clock signals according to the digital output signal. The subsampling phase detector performs rising-edge sampling and falling-edge sampling on an output signal of the voltage-controlled oscillator according to the plurality of sampling clock signals and the selection signal. Embodiments of the present invention achieve extremely low jitter and low in-band fractional spurs while occupying a very small area, and may be widely applied in the field of electronic circuit technology.
Glycosyl hydrolases, genes, vectors, host cells and applications [Granted Patent]
糖基水解酶、基因、載體、宿主細胞和應用 [授權專利]
Publication No.:
CN117660416B
Publication Date:
2026-07-27
Applicant(s):
北京中醫藥大學；澳門大學; Beijing University of Chinese Medicine; University of Macau
Inventor(s):
史社坡；劉曉；萬建波；羅源；張蓓蓓；王娟; Shi Shepo; Liu Xiao; Wan Jianbo; Luo Yuan; Zhang Beibei; Wang Juan
Technology Field(s):
生物技術; Biotechnology
The present invention discloses a glycoside hydrolase, a gene, a vector, a host cell, and applications thereof. The glycoside hydrolase is selected from the following: (a) a glycoside hydrolase comprising the amino acid sequence shown in SEQ ID NO: 1; and (b) a glycoside hydrolase derived from (a), in which one or more amino acids in the amino acid sequence shown in SEQ ID NO: 1 have been substituted, deleted, or added, and which retains equivalent functionality. The glycoside hydrolase of the present invention is capable of selectively hydrolyzing the glucosyl group at the C-3 position of PPD-type ginsenosides.
Publication No.:
CN117660416B
Publication Date:
2026-07-27
Applicant(s):
北京中醫藥大學；澳門大學; Beijing University of Chinese Medicine; University of Macau
Inventor(s):
史社坡；劉曉；萬建波；羅源；張蓓蓓；王娟; Shi Shepo; Liu Xiao; Wan Jianbo; Luo Yuan; Zhang Beibei; Wang Juan
Technology Field(s):
生物技術; Biotechnology
The present invention discloses a glycoside hydrolase, a gene, a vector, a host cell, and applications thereof. The glycoside hydrolase is selected from the following: (a) a glycoside hydrolase comprising the amino acid sequence shown in SEQ ID NO: 1; and (b) a glycoside hydrolase derived from (a), in which one or more amino acids in the amino acid sequence shown in SEQ ID NO: 1 have been substituted, deleted, or added, and which retains equivalent functionality. The glycoside hydrolase of the present invention is capable of selectively hydrolyzing the glucosyl group at the C-3 position of PPD-type ginsenosides.
An in-memory computing macro for neural network training
一種用於神經網路訓練的存內計算宏
Publication No.:
CN122431724A
Publication Date:
2026-07-27
Applicant(s):
澳門大學; University of Macau
Inventor(s):
於維翰；王振宇；阮家惲；麥沛然；馬許願; Yu Weihan; Wang Zhenyu; Ruan Jia Yun; Mai Peiran; Rui Paulo da Silva Martins
Technology Field(s):
電腦技術; Computer technology
An embodiment of the present application provides a compute-in-memory macro for neural network training, belonging to the technical field of compute-in-memory technology. The method includes: the compute-in-memory macro comprises an exponent processing module and an exponent-exclusive accumulation module, wherein the exponent-exclusive accumulation module comprises an exponent-to-one-hot addend decoder and an addend-compression adder tree; the exponent processing module is connected to the exponent-to-one-hot addend decoder, and the exponent-to-one-hot addend decoder is connected to the addend-compression adder tree. The exponent processing module is configured to perform exponentiation on prestored weights in logarithmic format to obtain a plurality of exponentiation results. The exponent-to-one-hot addend decoder is configured to perform exponent decoding on the exponentiation results to obtain a plurality of integer results. The addend-compression adder tree is configured to perform an accumulation-and-multiplication operation on the integer results to obtain a target result value. The embodiments of the present application can improve data-compression capability and the dynamic range of gradient values while maintaining the training accuracy of the neural network.
Publication No.:
CN122431724A
Publication Date:
2026-07-27
Applicant(s):
澳門大學; University of Macau
Inventor(s):
於維翰；王振宇；阮家惲；麥沛然；馬許願; Yu Weihan; Wang Zhenyu; Ruan Jia Yun; Mai Peiran; Rui Paulo da Silva Martins
Technology Field(s):
電腦技術; Computer technology
An embodiment of the present application provides a compute-in-memory macro for neural network training, belonging to the technical field of compute-in-memory technology. The method includes: the compute-in-memory macro comprises an exponent processing module and an exponent-exclusive accumulation module, wherein the exponent-exclusive accumulation module comprises an exponent-to-one-hot addend decoder and an addend-compression adder tree; the exponent processing module is connected to the exponent-to-one-hot addend decoder, and the exponent-to-one-hot addend decoder is connected to the addend-compression adder tree. The exponent processing module is configured to perform exponentiation on prestored weights in logarithmic format to obtain a plurality of exponentiation results. The exponent-to-one-hot addend decoder is configured to perform exponent decoding on the exponentiation results to obtain a plurality of integer results. The addend-compression adder tree is configured to perform an accumulation-and-multiplication operation on the integer results to obtain a target result value. The embodiments of the present application can improve data-compression capability and the dynamic range of gradient values while maintaining the training accuracy of the neural network.