Latest UM Patents (2026-08-10)

A high-rigidity carrier for promoting growth of anaerobic ammonium oxidation biofilm and its preparation method and application
一種高剛度且促厭氧氨氧化生物膜生長的載體及其製備方法和應用
Publication No.: CN122520241A
Publication Date: 2026-08-07
Applicant(s): 澳門大學; University of Macau
Inventor(s): 寄博華;鄭實嵩;黃瀅;郝天偉; Ji Bohua;Zheng Shisong;Huang Ying;Hao Tianwei
Technology Field(s): 環境技術 Environmental technology
The present invention discloses a high-rigidity carrier that promotes the growth of anammox biofilms, as well as a preparation method and application thereof, belonging to the field of biological wastewater treatment. The carrier has a cylindrical structure with an internal four-directional radial support structure and is made of polyamide. It is fabricated layer by layer using selective laser sintering (SLS) three-dimensional printing technology. After cleaning and drying, the carrier is introduced into an anammox bioreactor, where it supports the attachment of anammox biofilms and enables the anammox reaction. Through structural optimization and a three-dimensional printing process, the invention improves the structural rigidity and batch-to-batch consistency of the carrier. It is suitable for fixed-bed or fluidized-bed bioreactors and offers high stability, rapid start-up, and efficient nitrogen removal.

A fast video drone-satellite geographical positioning method based on bird’s-eye view transformation
一種基於鳥瞰視角變換的快速視頻無人機-衛星地理定位方法
Publication No.: CN122524052A
Publication Date: 2026-08-07
Applicant(s): 橫琴粵澳深度合作區澳門大學高等研究院;艾歐萬科技(珠海橫琴)有限公司; University of Macau Advanced Research Institute in Hengqin (HUMRI); IoV Technology (Hengqin, Zhuhai) Co., Ltd.
Inventor(s): 黃少飛;鄭哲東;鞠豪;萬千; Huang Shaofei; Zheng Zhedong; Ju Hao; Wan, Qian
Technology Field(s): 測量、電腦技術 Measurement, Computer technology
The present invention relates to the fields of artificial intelligence and computer vision, and discloses a fast video-based UAV-to-satellite geolocalization method based on bird’s-eye-view transformation. The method includes extracting key frames having different viewpoints from a UAV video and performing three-dimensional geometric reconstruction to obtain a three-dimensional scene representation; generating multiple bird’s-eye-view UAV images with different coverage areas and viewing scales; and using the multiple bird’s-eye-view UAV images as a joint query input for matching against a satellite image database. Similarities between the images are calculated to obtain final satellite-image matching results and thereby determine the location. The method can significantly reduce the effect of single-frame occlusion on geolocalization results and improve localization stability in complex urban environments and low-altitude flight scenarios. It better preserves geographic structural details while reducing image distortion and blurring. In addition, the viewpoint discrepancy between the query domain and the image-database domain is substantially reduced, facilitating subsequent feature matching and enabling faster, more accurate cross-view retrieval.

High-speed and low-power hybrid dynamic comparator that takes into account low power supply voltage and low latency
兼顧低電源電壓和低延時的高速低功耗混合動態比較器
Publication No.: CN122512901A
Publication Date: 2026-08-04
Applicant(s): 中國南方電網有限責任公司超高壓輸電公司電力科研院;橫琴粵澳深度合作區澳門大學高等研究院; Electric Power Research Institute, China Southern Power Grid Co., Ltd.; University of Macau Advanced Research Institute in Hengqin (HUMRI)
Inventor(s): 崔彥捷;段振輝;鄧軍;周海濱;諸嫣;陳知行;馬許願;潘志城;謝志成;張晉寅;孫勇;伍衡; Cui Yanjie; Duan Zhenhui; Deng Jun; Zhou Haibin; Zhu Yan; Chen Zhixing; Rui Paulo da Silva Martins; Pan Zhicheng; Xie Zhicheng; Zhang Jinyin; Sun Yong; Wu Heng
Technology Field(s): 基本通訊流程 Basic communication processes
The present invention relates to the field of integrated circuits and discloses a high-speed, low-power hybrid dynamic comparator that achieves both low supply-voltage operation and low latency. The comparator comprises a preamplifier section, mainly including a first tail transistor M1, input transistors M3 and M4, and transmission gates; and a latch section, mainly including a second tail transistor M2, transistors M5 and M6, and cross-coupled transistors M7 and M8. The two sections are connected through differential nodes VOP and VON, and the conduction states of M1 and M2 are controlled by a clock signal. The comparator reduces the number of stacked transistors between the supply voltage and ground, thereby facilitating operation at low supply voltages. During a first clock phase, the input differential signal is amplified and directly stored on parasitic capacitances associated with the latch stage. During a second clock phase, the comparator directly enters the latch regeneration process, thereby reducing clock-to-output delay and maintaining stable delay over a wide input common-mode voltage range.